Bell Labs Platform & ASIC Research Co-op

Position: Bell Labs Platform & ASIC Research Co-op
Number of Position(s): 1
Duration: 4 Months 
Date: January 12 – May 22, 2026
Location: On-site (New Jersey, USA)

EDUCATIONAL RECOMMENDATIONS

Currently a candidate for a PhD degree in Computer Science, Electrical Engineering, Computer Engineering, or Engineering in VLSI and telecommunication or related field with an accredited school in the US. Minimum GPA 3.0.

*Highly qualified Master's students will be considered

• Advanced RTL development skills and fluent in HDL (SystemVerilog and VHDL) and/or HLS (High-level Synthesis)
• Experience in ASIC physical design tools: Cadence (Innovus, Spectre, Virtuoso) and Synopsys (VCS, ICC)
• Knowledge in micro-architecture, gate or RTL-level design optimization, timing closure analysis, and/or mixed-signal circuit design
• AI/ML programming frameworks: TensorFlow, PyTorch, Keras, etc.
• Background in compiler, operating system, and kernel-level embedded software programming for parallel systems

As a part of our team, you will:

• Work with seasoned Bell Labs researchers on the design and development of ASIC and/or proof-of-concept platform.
• Participate in a research project, work with mentor(s) to define, develop, and conduct a research project, and attend research talks in various technology areas.
• The SoC research project will be in any of the following areas:
  • Machine Learning acceleration
  • Digital signal processing and accelerator for 5G/6G communication systems
  • Cloud-based radio access network