Design Engineering Intern

The Silicon Labs Summer Internship Program

At Silicon Labs, our internship program offers students the opportunity to do meaningful, hands-on work that directly impacts the future of connected devices. As an intern, you’ll contribute to real projects, collaborate with world-class engineers, and gain exposure to the full product lifecycle, from research and design to testing and integration. Our program also includes professional development workshops, networking events, and mentorship to help you grow both technically and professionally.  Our goal is to help you build on your skills, gain hands-on experience, and explore the potential of a future career with Silicon Labs.Learn more about ourSummer Internship Program.

Meet the Team

You’ll join the Subsystems R&D – Digital IP team, which develops intellectual property (IP) that forms the backbone of Silicon Labs’ chip infrastructure. The team focuses on building and optimizing digital IP blocks such as chip interconnect, DMA, memory controllers, and caches while advancing new accelerators, including AI-focused designs. This work enables highly efficient, low-power SoCs and creates opportunities to explore cutting-edge innovations in digital system design.

Responsibilities

• Contribute to the design, development, and verification of digital IP blocks for internal chip infrastructure.

• Apply Verilog/SystemVerilog to model, simulate, and validate digital hardware components.

• Support synthesis and static timing analysis to ensure efficient and reliable chip integration.

• Collaborate with engineers to define architecture and implement system-level features.

• Participate in accelerator development projects, with opportunities to explore emerging applications such as AI.

• Document and present findings to the team.

Skills You Need

Minimum Qualifications:

• Currently pursuing a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.

• Coursework or project experience in digital design and computer architecture.

• Proficiency with Verilog or SystemVerilog for digital hardware design.

• Familiarity with synthesis tools and static timing analysis workflows.

The following qualifications will be considered a plus: 

• Hands-on experience with FPGA design and prototyping.

• Programming knowledge in Python or C/C++ for automation or design support.

• Prior project work integrating digital IP into larger SoC or hardware systems.

Perks and Program Offerings

You can look forward to the following:

• Hybrid work schedule 

• Free downtown parking 

• Full access to onsite gym 

• Free snacks and beverages 

• Weekly Lunch and Learn sessions

• Weekly 1 x 1’s with your manager and mentor

• Weekly "Meet a Former Intern” coffee chats 

• Monthly wellness offerings 

• Monthly company updates with our CEO 

• Inclusion in social events with various teams and Employee Resource Groups (ERGs)

• Participation in select L&D offerings 

• Virtual events with global intern class 

• End of summer presentation of your project during Intern Symposium

The annualized base pay range for this role is expected to be between $79,040 ($38/HR) to $95,680 ($46/HR) USD. Actual base pay could vary based on factors including but not limited to experience, geographic location where work will be performed and applicant’s skill set. The base pay is just one component of the total compensation package for employees.  Other components may include a sign on bonus.

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