ASIC Design and Verification Engineer Intern

Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve our billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services. We are looking for talented individuals to join us for an internship in 2026. Internships at ByteDance aim to offer students industry exposure and hands-on experience. Watch your ambitions become reality as your inspiration brings infinite opportunities at ByteDance. Candidates can apply to a maximum of two positions and will be considered for jobs in the order you apply. The application limit is applicable to ByteDance and its affiliates' jobs globally. Applications will be reviewed on a rolling basis - we encourage you to apply early. Successful candidates must be able to commit to at least 3 months long internship period. Internships at ByteDance aim to provide students with hands-on experience in developing fundamental skills and exploring potential career paths. A vibrant blend of social events and enriching development workshops will be available for you to explore. Here, you will utilize your knowledge in real-world scenarios while laying a strong foundation for personal and professional growth. It runs for 12 weeks. Candidates can apply to a maximum of two positions and will be considered for jobs in the order you apply. The application limit is applicable to ByteDance and its affiliates' jobs globally. Applications will be reviewed on a rolling basis. We encourage you to apply as early as possible. Please state your availability clearly in your resume (Start date, End date). Summer Start Dates: - May 11th, 2026 - May 18th, 2026 - May 26th, 2026 - June 8th, 2026 - June 22nd, 2026 Responsibilities - As an ASIC Design Engineer in this Video Silicon IP team, we work closely with architecture, algorithm and verification team to build high performance and low power video processing IPs. Apply your knowledge of computer architecture and ASIC design to create ASIC design for compressing, processing still images and videos. - As a Design Verification engineer, you will be taking on an important role in helping deliver a Video Codec IP by generating test benches and running simulations. You will interface with architects and ASIC/FPGA design engineers to develop test plans, lead bug tracking, and automation of regression testing. Minimum Qualifications: - Currently pursuing an Undergraduate/Master in computer science/electrical engineering or a related technical discipline - Knowledge of Video Codecs - Experience with RTL design (SystemVerilog) or High level Synthesis (HLS) - Experience with UVM methodology, SystemC, or DPI - Good programming skills in Python for task automation - Must be able to commit to a 12-week full-time work period during Summer 2026. By submitting an application for this role, you accept and agree to our global applicant privacy policy, which may be accessed here: https://jobs.bytedance.com/en/legal/privacy