IC Package Design Research Intern

Position:IC Package Design Research Intern
Number of Positions: 1
Duration: 10 weeks
Date: June 1 - August 7, 2026
Location: On-site

Educational Recommendations:
Currently a candidate for an MS or PhD in electrical engineering, materials science, applied physics, or a related field at an accredited school in the USA. 

• The candidate must have a solid knowledge of multi-physics as it relates to advanced IC packaging, including EM, SI/PI, thermal, and mechanical.
• The candidate must have demonstrated knowledge of RF, expertise in high-speed interconnect design and simulation, and hands-on experience in performing high-frequency measurements.
• The candidate must be able to contribute effectively and efficiently within a larger team, demonstrating strong communication skills and partnering with other groups in Nokia Bell Labs.
• Expertise in:
  • IC packaging techniques, materials, and microelectronics assembly process flows
  • Schematic capture and substrate layout design (Cadence or Siemens)
• Familiarity with:
  • Circuit design and simulation software (Keysight ADS, Cadence AWR, or equivalent)
  • RF test equipment and component characterization
    
     

As part of our team, you will:

• Work directly with a cross-functional Nokia Bell Labs R&D team and Nokia business units to define novel architectures, design, simulate, and characterize state-of-the-art semiconductor packaging solutions operating in the mm-Wave and Terahertz spectrums.
• Lead efforts to identify key areas and innovative materials in advanced IC packaging.